Making Verification Methodology and Tool Decisions
This is the second of a three parts series. Part 1 can be found here
Are you itching to try a new methodology or technology to enhance your existing processes? Are you certain that management will resist change? Read on and learn how to use the new field of metric-driven engineering to objectively justify your decisions using automatically gathered data.
It happens all the time in engineering. A new process or methodology comes along. It looks attractive, your gut tells you this is the way to go, but adopting it requires one the big three 'scary' things:
- Risk (We've never done this before, will it work?)
- Cultural change (You want my designers to write assertions?)
- Spending money (Are you sure that tool will pay for itself?)
|
Cadence Hot IP
Related Articles
- Formal-based methodology cuts digital design IP verification time
- Methodology Independent Exhaustive Constraint Solver for Random Verification and Regression Generation
- Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs
- Metric Driven Verification of Reconfigurable Memory Controller IPs Using UVM Methodology for Improved Verification Effectiveness and Reusability
- Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC
New Articles
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |