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Verification methodologies keep pace with complex IP
By Roger Witlox, Ronald Heijmans and Chris Wieckardt, NXP Semiconductors
August 14, 2007 -- edadesignline.com
The verification of IP cores continues getting more complex and time consuming, especially processor cores, such as CPUs, floating-point units, and digital signal processors, the subject of this story. The challenge is to design and verify a new embedded vector processor with significant enhancements over its predecessor. This has been achieved by NXP's AdelanteTM VD3204x Embedded Vector DSP family.
In order to improve the quality of our DSP technology at DSP-IC, a department within NXP Semiconductors (formerly Philips Semiconductors), the attention for verification turned to tools and techniques that might advance the verification process. The experiences are shared in the coming paragraphs.
August 14, 2007 -- edadesignline.com
The verification of IP cores continues getting more complex and time consuming, especially processor cores, such as CPUs, floating-point units, and digital signal processors, the subject of this story. The challenge is to design and verify a new embedded vector processor with significant enhancements over its predecessor. This has been achieved by NXP's AdelanteTM VD3204x Embedded Vector DSP family.
In order to improve the quality of our DSP technology at DSP-IC, a department within NXP Semiconductors (formerly Philips Semiconductors), the attention for verification turned to tools and techniques that might advance the verification process. The experiences are shared in the coming paragraphs.
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