Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
Practical design considerations -- Ethernet vs. RapidIO standards
August 15, 2007 -- pldesignline.com
Engineers often discover ways to leverage technology in applications for which it was never intended. Sometimes the fit is "good enough" and the resulting economies of scale are sufficient to make the extended technology implementation successful. But the desire to use a familiar technology runs the risk of stretching the technology beyond its capabilities, complicating designs and creating unforeseen problems.
For example, Ethernet is frequently considered a prime candidate for the convergence protocol in system-level fabrics, yet comparing the familiar Ethernet to the RapidIO specification for board- and chassis-level applications can be surprising.
Ethernet was designed for large networks with many endpoints, each with a powerful processor available for protocol stack processing. RapidIO technology was designed specifically for embedded in-the-box and chassis control plane applications, and emphasizes reliability with minimal latency, limited software dependence, protocol extensibility, and simplified switching that provides effective data rates from 667 Mbps to 30 Gbps. Additionally, RapidIO technology features hardware-based protocol processing, support for read/write operations, messaging, data streaming, HWQoS, data plane extensions, and protocol encapsulation.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- PCIe 5.0 vs. Emerging Protocol Standards - Will PCIe 5.0 Become Ubiquitous in Tomorrow's SoCs?
- A Look at New Open Standards to Improve Reliability and Redundancy of Automotive Ethernet
- PCI Express vs. Ethernet: A showdown or coexistence?
- Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC
- Backplane tutorial: RapidIO, PCIe and Ethernet
New Articles
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Why RISC-V is a viable option for safety-critical applications
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- An Outline of the Semiconductor Chip Design Flow
- Synthesis Methodology & Netlist Qualification