Multi-Core Processors: Driving the Evolution of Automotive Electronics Architectures
By Patrick Leteinturier, Infineon Technologies
(09/16/07, 06:00:00 PM EDT) -- Embedded.com
The electronic content of the automobile is expanding dramatically, driven by several concurrent forces, including consumer demand for entertainment systems and convenience functions, the addition of enhanced safety features, and government emission control regulations.
Consequently, engineers are working to raise the functionality of electronics, while simultaneously devising strategies to improve fault tolerance and provide fail-safe operation of all critical systems.
On average, a new passenger vehicle today features about 80 integrated and networked systems. And while the control of such systems as powertrain, ABS (Anti-lock Braking System), airbag control and body electronics functions has traditionally been self-contained, a great deal of value can be added by exchanging data between systems.
For example, traction control systems optimize the grip of tires on the road surface, which requires that the brakes be modulated and the powertrain system retard engine torque at the same time. This can be accomplished relatively easily through a simple serial communications link between the ABS ECU (electronic control unit) and the powertrain ECU.
However, as the number of interconnects and gateways between different systems expands, the growing number of interfaces and likely bottlenecks increases the potential that the overall vehicle electronics network may grow too complex.
Overloaded networks are not efficient. They require increased testing and validation, the complexity increases the possibility of system faults, and total system cost is not optimal. A solution to this growing complexity is evolution of the vehicle electronics into a domain architecture connected by a backbone (Figure 1 below).
E-mail This Article | Printer-Friendly Page |
Related Articles
- Using sub-RISC processors in next generation customizable multi-core designs: Part 1
- Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device
- Evaluating the performance of multi-core processors - Part 2
- Evaluating the performance of multi-core processors - Part 1
- Transcoding video with parallel programming on multi-core processors
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)