English
Viewpoint: RTL-ers should move to ESL
Tom Sandoval, Calypto Design Systems
(10/19/2007 2:15 PM EDT) -- EE Times
Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented. There were methodology experts within electronics companies whose sole responsibility was to move design teams to using RTL design methods. It was this focus that enabled the methodology shift the industry experienced and changed the way chips were designed.
Back then, the average chip had tens of thousands of gates and took 18 to 24 months to design. Fast forward to 2007 and, while the average gate count is now in the tens of millions, design cycle requirements have been slashed to six to nine months. Still, the majority of U.S. design teams are using a design methodology similar to what was used in the 1990s.
While RTL design was and still is an important engineering methodology development, new technologies and standards are forcing continued evolution. But, what happened to our methodology experts?
(10/19/2007 2:15 PM EDT) -- EE Times
Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented. There were methodology experts within electronics companies whose sole responsibility was to move design teams to using RTL design methods. It was this focus that enabled the methodology shift the industry experienced and changed the way chips were designed.
Back then, the average chip had tens of thousands of gates and took 18 to 24 months to design. Fast forward to 2007 and, while the average gate count is now in the tens of millions, design cycle requirements have been slashed to six to nine months. Still, the majority of U.S. design teams are using a design methodology similar to what was used in the 1990s.
While RTL design was and still is an important engineering methodology development, new technologies and standards are forcing continued evolution. But, what happened to our methodology experts?
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow