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Accelerating Functional Verification
Interactive Methodology Opens Door to New Efficiencies
By John Brennan and Dave Tokic, Cadence Design Systems
October 29, 2007 -- edadesignline.com
SoC design isn't getting any easier. Escalating IC densities, rising design complexity and increasingly intricate software interactions are conspiring to reduce predictability and drive up cycle-time risk. At the same time the growing use of software-enabled customizations is quickly rendering existing methodologies obsolete. Relentless demand to reduce power, particularly in portable consumer applications, has reshuffled priorities within the design flow. Complicating these trends, few teams have the design experience in-house to handle and manage these rapid changes.
In some areas of SoC design, the EDA industry has achieved major advances over the past few years. For designers developing digital circuits, for instance, automated routing has greatly simplified the manual layout process. The challenges are a little bit more daunting, however, for engineers tackling analog/mixed-signal design or functional verification. Cross domain verification is often ineffective and requires manual intervention. And the escalating data sets and long simulation runtimes that accompany more complex SoC designs complicate modeling, extraction and re-simulation of parasitics and threaten design predictability.
The most imposing obstacle to better designer productivity and improved SoC predictability lies in functional verification. Studies clearly indicate that verification is the single most time-consuming task in any design flow. Many new tools and technologies introduced over the last few years have promised to address these rising verification challenges. But understanding and applying them often undermines team productivity. Few engineers, for instance, have the time to read a 2,000-page methodology manual or explore through repeated trial and error how to get up to speed on a new tool. So the real challenge for many design teams today is moving beyond the traditional tool silo approach where engineers learn about a single tool at one time, and reaching a point where they can easily collect information from multiple tools in a comprehensive way that enables a coverage-driven verification process.
By John Brennan and Dave Tokic, Cadence Design Systems
October 29, 2007 -- edadesignline.com
SoC design isn't getting any easier. Escalating IC densities, rising design complexity and increasingly intricate software interactions are conspiring to reduce predictability and drive up cycle-time risk. At the same time the growing use of software-enabled customizations is quickly rendering existing methodologies obsolete. Relentless demand to reduce power, particularly in portable consumer applications, has reshuffled priorities within the design flow. Complicating these trends, few teams have the design experience in-house to handle and manage these rapid changes.
In some areas of SoC design, the EDA industry has achieved major advances over the past few years. For designers developing digital circuits, for instance, automated routing has greatly simplified the manual layout process. The challenges are a little bit more daunting, however, for engineers tackling analog/mixed-signal design or functional verification. Cross domain verification is often ineffective and requires manual intervention. And the escalating data sets and long simulation runtimes that accompany more complex SoC designs complicate modeling, extraction and re-simulation of parasitics and threaten design predictability.
The most imposing obstacle to better designer productivity and improved SoC predictability lies in functional verification. Studies clearly indicate that verification is the single most time-consuming task in any design flow. Many new tools and technologies introduced over the last few years have promised to address these rising verification challenges. But understanding and applying them often undermines team productivity. Few engineers, for instance, have the time to read a 2,000-page methodology manual or explore through repeated trial and error how to get up to speed on a new tool. So the real challenge for many design teams today is moving beyond the traditional tool silo approach where engineers learn about a single tool at one time, and reaching a point where they can easily collect information from multiple tools in a comprehensive way that enables a coverage-driven verification process.
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