Using Serial RapidIO for FPGA co-processing
November 08, 2007 -- dspdesignline.com
Today's ever increasing demand for high-speed communication and super-fast computing in support of "triple-play" applications is creating new challenges for system developers, algorithm developers and hardware engineers alike who need to draw together a multitude of standards, components and networking equipment. At the same time, developers need to keep pace with increasing demands for performance while keeping costs low. These feats can be accomplished by leveraging Serial RapidIO-enabled FPGAs as DSP co-processors.
Because triple-play applications unite voice, video and data, development and system optimization strategies must be parameterized using newer algorithms. Specific challenges that developers need to address include building scalable and extensible architectures, supporting distributed processing, using standards-based design, and optimizing for performance and cost.
A closer look at these challenges reveals two themes: Connectivity—which is essentially "fast" data movement across devices, boards and systems—and Computing power—i.e., the individual processing resources that are available in the devices, boards and systems—address the needs of the application.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Using parallel FFT for multi-gigahertz FPGA signal processing
- How to achieve 1 trillion floating-point operations-per-second in an FPGA
- Rapid debug of serial buses in FPGAs
- A configurable FPGA-based multi-channel high-definition Video Processing Platform
- How to tackle serial backplane challenges with high-performance FPGA designs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)