Partitioning applications across multiple cores

By Stephen Cole & David Kramer, Networking & Multimedia Group, Freescale Semiconductor
(12/07/2007 2:57 PM EST) -- EE Times

Multi-core mania has definitely hit the embedded networking market, but as the dust begins to settle it has become clear that many important architectural details need to be examined closely before decisions are made about how to partition applications across multiple cores.

The multi-core processors used today for networking equipment commonly target enterprise-level access routers, but the ones being marketed today offer much more than just layer-2 and layer-3 routing. Many higher-layer services, such as layers 4 through 7, are being added by networking companies trying to differentiate their products while absorbing into their equipment some of the specialized appliances that have been added to networks in the past, thus reducing the operating expenses incurred by diversified networking solutions. Many of the systems currently on the market are running their control and data planes, as well as all additional services, on single-core processors. However, single-cores are hitting a frequency ceiling set by system power budgets, a problem that simply can't be solved by transistor technology. Thus, the need for more performance and more widely differentiated services in next-generation systems makes these systems ideal candidates for multi-core devices, offering a way for system vendors to increase system performance and add new services while staying within the power budgets so often driven by system locations and end-users' pocketbooks. Multi-core processors offer outstanding performance per watt by simply dialing back core frequencies to use less aggressive transistor technology, thus saving die area and reducing static and dynamic power consumption.

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