English
Efficient testbench implementation for verification proposed by Synopsys staffer
K.C. Krishnadas, EE Times:
(12/21/2007 7:57 AM EST)
BENGALURU, India -- Identifying hidden bugs in the verification phase of configurable host controller IP, such as the host controller supporting multiple protocols (SD/MMC/CEATA) is challenging as some bugs are deeply embedded and can be detected only with a sequence of transactions like error transaction followed by normal transaction.
Verification engineers develop discrete error tests to cover error scenarios and these are run separately but this does not always detect sequence dependent bugs as the testbench may not be capable of generating a mix of normal and error transactions, or as the testbench driver may not be capable of injecting the errors and automatically recover to the normal state to support the stream of random transactions that include normal and error transactions.
Pusuluri Giri Kumar from Synopsys (India) has devised a solution whose focus lies with the design and implementation of the transaction generation model and the testbench driver, with the testbench based on reusable verification methodology guidelines and said he was able to detect hidden bugs when verifying host controller IP for mobile storage applications.
"Emerging mobile storage technologies enable high capacity storage devices (compliant to protocols like SD, MMC and CEATA to be integrated into the devices like digital cameras, MP3 players. The physical interface for these memory devices remains the same but the communication protocol varies; hence the host controllers should be configurable to be interfaced with mobile storage devices.
(12/21/2007 7:57 AM EST)
BENGALURU, India -- Identifying hidden bugs in the verification phase of configurable host controller IP, such as the host controller supporting multiple protocols (SD/MMC/CEATA) is challenging as some bugs are deeply embedded and can be detected only with a sequence of transactions like error transaction followed by normal transaction.
Verification engineers develop discrete error tests to cover error scenarios and these are run separately but this does not always detect sequence dependent bugs as the testbench may not be capable of generating a mix of normal and error transactions, or as the testbench driver may not be capable of injecting the errors and automatically recover to the normal state to support the stream of random transactions that include normal and error transactions.
Pusuluri Giri Kumar from Synopsys (India) has devised a solution whose focus lies with the design and implementation of the transaction generation model and the testbench driver, with the testbench based on reusable verification methodology guidelines and said he was able to detect hidden bugs when verifying host controller IP for mobile storage applications.
"Emerging mobile storage technologies enable high capacity storage devices (compliant to protocols like SD, MMC and CEATA to be integrated into the devices like digital cameras, MP3 players. The physical interface for these memory devices remains the same but the communication protocol varies; hence the host controllers should be configurable to be interfaced with mobile storage devices.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Synopsys, Inc. Hot IP
Related Articles
- A formal-based approach for efficient RISC-V processor verification
- Efficient Verification of RISC-V processors
- Easing PCIe 6.0 Integration from Design to Implementation
- Automotive Design Needs Efficient Verification to Survive
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)