English
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
The art of FPGA construction
By Gina R. Smith, Brown-Smith Research and Development Laboratory Inc.
(01/06/08, 02:00:00 PM EST) -- Embedded.com
Over the last several years, the use of FPGAs has greatly increased in military and commercial products. They can be found in primary and secondary surveillance radar, satellite communication, automotive, manufacturing, and many other types of products. While the FPGA development process is second nature to embedded systems designers experienced in implementing digital designs on an FPGA, it can be confusing and difficult for the rest of us. Good communication is important when technical leads, supervisors, managers, or systems engineers interface with FPGA designers.
The key to good communication is having an understanding of the development process. A solid understanding will help you comprehend and extract relevant information for status reports, define schedule tasks, and allocate appropriate resources and time. There have been many times when my FPGA knowledge has allowed me to detect and correct errors, such as wrong part numbers or misuse of terms and terminology found in requirements and other documents.
Regardless of your final product, FPGA designers must follow the same basic process. The FPGA development stages are design, simulation, synthesis, and implementation, as shown in Figure 1. The design process involves converting the requirements into a format that represents the desired digital function(s). Common design formats are schematic capture, hardware description language (HDL), or a combination of the two. While each method has its advantages and disadvantages, HDLs generally offer the greatest design flexibility.
(01/06/08, 02:00:00 PM EST) -- Embedded.com
Over the last several years, the use of FPGAs has greatly increased in military and commercial products. They can be found in primary and secondary surveillance radar, satellite communication, automotive, manufacturing, and many other types of products. While the FPGA development process is second nature to embedded systems designers experienced in implementing digital designs on an FPGA, it can be confusing and difficult for the rest of us. Good communication is important when technical leads, supervisors, managers, or systems engineers interface with FPGA designers.
The key to good communication is having an understanding of the development process. A solid understanding will help you comprehend and extract relevant information for status reports, define schedule tasks, and allocate appropriate resources and time. There have been many times when my FPGA knowledge has allowed me to detect and correct errors, such as wrong part numbers or misuse of terms and terminology found in requirements and other documents.
Regardless of your final product, FPGA designers must follow the same basic process. The FPGA development stages are design, simulation, synthesis, and implementation, as shown in Figure 1. The design process involves converting the requirements into a format that represents the desired digital function(s). Common design formats are schematic capture, hardware description language (HDL), or a combination of the two. While each method has its advantages and disadvantages, HDLs generally offer the greatest design flexibility.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
- The rise of FPGA technology in High-Performance Computing
- Understanding Interface Analog-to-Digital Converters (ADCs) with DataStorm DAQ FPGA
- FPGA Market Trends with Next-Gen Technology
- eFPGA LUTs Will Outship FPGA LUTs Later This Decade
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- System Verilog Assertions Simplified
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
- Dynamic Memory Allocation and Fragmentation in C and C++
- Synthesis Methodology & Netlist Qualification