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Dealing with the challenges of integrating hardware and software verification
By Sean Smith, Chief Verification Architect, Denali Software Inc.
(01/04/08, 01:38:00 AM EST) -- Embedded.com
The design verification industry has leaped forward from its simplistic roots when directed stimulus was used to perform verification with HDL. The approach has now shifted to using advanced programming techniques to create richer and reusable models; directed random stimulus to reduce test case writing efforts; and functional and code coverage to measure verification progress objectively.
While these techniques and methodologies have improved design quality and verification efficiency, there is still work to accomplish, especially for complex chip designs.
Chip-design teams already have a good grasp of block- and chip-level verification. System-level verification is now the arena where the biggest challenges and opportunities lie. The verification community—made up of the EDA industry and its users—is investing heavily to find solutions for this. Why? Because of software drivers and firmware.
Today's silicon intellectual property (SIP) and SoCs are increasingly dependent on firmware and device drivers as key deliverables for the end solution. In the current scenario, a silicon or IP provider must invest substantial resources to provide software IP along with their SIP. Gone were the days of waiting for silicon to arrive before developing and debugging device drivers and embedded software.
Often, design teams use an equivalent or greater number of software engineers in proportion to hardware engineers because the industry needs to further integrate hardware and software implementation and debug. This article explores challenges and solutions in the closer integration of software development and validation with silicon design and verification.
(01/04/08, 01:38:00 AM EST) -- Embedded.com
The design verification industry has leaped forward from its simplistic roots when directed stimulus was used to perform verification with HDL. The approach has now shifted to using advanced programming techniques to create richer and reusable models; directed random stimulus to reduce test case writing efforts; and functional and code coverage to measure verification progress objectively.
While these techniques and methodologies have improved design quality and verification efficiency, there is still work to accomplish, especially for complex chip designs.
Chip-design teams already have a good grasp of block- and chip-level verification. System-level verification is now the arena where the biggest challenges and opportunities lie. The verification community—made up of the EDA industry and its users—is investing heavily to find solutions for this. Why? Because of software drivers and firmware.
Today's silicon intellectual property (SIP) and SoCs are increasingly dependent on firmware and device drivers as key deliverables for the end solution. In the current scenario, a silicon or IP provider must invest substantial resources to provide software IP along with their SIP. Gone were the days of waiting for silicon to arrive before developing and debugging device drivers and embedded software.
Often, design teams use an equivalent or greater number of software engineers in proportion to hardware engineers because the industry needs to further integrate hardware and software implementation and debug. This article explores challenges and solutions in the closer integration of software development and validation with silicon design and verification.
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