Single Flow for Interconnecting IP

By Mike Smith and Jo Anderson; Beach Solutions Ltd
June 20, 2008 -- edadesignline.com

The latest challenge facing SoC teams is the construction of a design flow that seamlessly combines:

A complex central Interconnect Matrix
Auto generation of a diverse range of system design views

In this article, we outline a flow, based around industry proven and emerging 'capture and auto generation' EDA solutions, which results in seamless interoperability between disparate tools and methods.

While, suppliers of Interconnect Matrix components provide complex architectures for hardware, the SoC team is also responsible for producing other associated design view outputs such as documentation and code for software development, test and verification. Ultimately the team is responsible for delivering a fully tested, documented and usable product " on time.

A central Interconnect Matrix allows a designer to create multiple memory maps and control communications paths based on specific master and slave combinations easily and quickly. The design and creation of an Interconnect Matrix component is well defined and tools providing suitable architectures are available, from companies such as Sonics, ARM, Arteris etc.

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