Low power design for analog/mixed signal IP

By Navraj Nandra, Synopsys
First published by EETimes Asia -- (June 24, 2008)

Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase. Starting with the techniques for lowering the power consumption in analog circuits such as operational amplifiers, this article will then focus on low power design for high-speed serial interconnects. Different architectures for output drivers and methods such as level shifting, for ac-coupled systems such as PCIe, Serial ATA and XAUI will be discussed.

System designers are influencing the specifications of high speed serial interconnects and a good example of this can be seen with the emerging standards for the USB protocol: LPM and HSIC. USB is prevalent as the high-speed serial interconnect in portable devices such as smart phones and mobile Internet devices. The goal of link power management (LPM) is to reduce power consumption of USB devices and hosts, potentially extending battery life by at least 20 percent. HSIC or "high speed inter-chip USB" allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Both will be reviewed in this article.

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