ESL handoff: closer than you think
edadesignline.com -- July 08, 2008
"ESL" is a hot topic these days. You get somewhat different definitions of ESL depending on whom you talk to, but the common theme is around having system-level design and verification environments (or processes) enabling co-design and co-verification of hardware and software. More narrowly, an ESL solution (or tool suite) can be thought of as a combination of tools used early in the design process to model architectures at high-levels of abstraction (C, C++ and SystemC), develop software and synthesize logic with a path to implementation and RTL verification.
Raising the level of design abstraction to increase engineering productivity has always been the "story of EDA". From the early days of SPICE/transistor-level design, then to gate-level/schematic-capture, and finally to RTL, each methodology transition has enabled 10-100x improvements in designer productivity. Since IC design transitioned to RTL about 15 years ago, designs have grown in size/complexity by 1-2 orders of magnitude. Many IP blocks today are larger than entire chips were back then. Although certain details have changed, the basic methodology has remained the same; if you deep-froze a capable Verilog RTL designer in 1993, and woke her up today, she could join a typical project on a Monday morning and be productive by Friday afternoon. The main reason is that all the design methodology developments have remained constrained within the domain of hardware design.
Development practices and methodologies, like life-forms, evolve according to Natural Selection. Today's hardware and software development methodologies became highly adapted to their respective environments, but the difficulty now is that the overall environment for electronics development has changed: the amount of software running on SoCs has increased dramatically, and to meet time-to-market goals designers are having to develop hardware and software in-parallel. The goal of ESL has always been to enable that, but the environments for hardware and software development are extremely different, with fundamentally different paradigms for specifying, implementing and verifying functionality. Despite the immense challenges associated with bridging between these two domains, in just the past 5 years however, there has been genuine progress, with EDA and electronics companies working together to develop new open-standards, new technologies, and new design methodologies to tackle the challenges of system-level design.
E-mail This Article | Printer-Friendly Page |
|
Cadence Hot IP
Related Articles
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- Royalty-based libraries cost more than you think
- Procrastination Is All You Need: Exponent Indexed Accumulators for Floating Point, Posits and Logarithmic Numbers
- A closer look at security verification for RISC-V processors
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)