Prototyping with the Spartan-3A DSP starter platform
dspdesignline.com (July 27, 2008)
Have you ever had a great idea for the next killer FPGA application but struggled to find the right prototyping hardware that would allow you to prove out your concept? You're not alone. Finding the perfect development platform is not easy. Boards are often designed more for demonstration than development, leaving designers with little flexibility and limited access to FPGA I/O pins.
With the recent introduction of the Xilinx Spartan-3A DSP FPGA family, Xilinx has created a unique, low-cost, prototype-friendly starter platform to ease your application development. Through the EXP expansion interface included on the board, you can add application-specific daughter cards to customize the board's feature set for your prototype needs.
In this article, I'll review the EXP standard, showing you why it's FPGA-friendly and able to meet your most demanding expansion needs. We'll look at several of the EXP modules currently available and see how they can be used to easily create video, embedded, and communications processing applications around the Spartan-3A DSP. You'll see how the EXP specification, the Spartan-3A DSP Starter Platform, and the EXP add-on modules can combine to quickly and cost-effectively provide you with a useful prototype system.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Virtual Prototyping Platform with Flash Memory
- Product how-to: DSP/FPGA platform for video surveillance
- Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment
- Producing an Effective WLAN Prototyping Platform
- Writing a modular Audio Post Processing DSP algorithm
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)