NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
How to manage dynamic power in a microcontroller using its non-maskable interrupt
How to manage dynamic power in a microcontroller using its non-maskable interrupt
By Ajit Basarur, Shantanu Prasad Prabhudesai, and Nazmul Hoda, Ittiam Systems
pldesignline.com (August 06, 2008)
Abstract
As portable systems become increasingly power-conscious, the need for smart power management becomes equally important. Besides the main processor, an auxiliary Microcontroller Unit (MCU) often resides on such systems to take care of house keeping activities such as various user interfaces and a real-time clock (RTC), which has to tick even when the system is powered off.
In this article, we suggest a mechanism to implement power management scheme for the MCU based on system switch on and off states by using its non-maskable interrupt (NMI) pin.
1. Typical embedded system overview.
(Click this image to view a larger, more detailed version)
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- How to use CPLDs to manage average power consumption in portable applications
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
- How to manage changing IP in an evolving SoC design
- How NoCs ace power management and functional safety in SoCs
- How eNVM Helps Power Controllers Be Smarter
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)