Algorithmic synthesis improves designers' efficiency

By Vinod Kathrail, Synfora Inc.
August 25, 2008 -- edadesignline.com

Introduction

Designers of consumer product ICs are faced today with the challenges of rapidly increasing complexity, a market with high expectations, and static price points. To stay competitive, design teams must find a way to reduce the cost and improve the efficiency of IC design. This dilemma has gone beyond the capacity of existing methodologies, and the industry is in urgent need of a new approach. Most agree that the solution to improving cost and efficiency is to move to a higher level of abstraction - but what is the best route to get there?

Algorithmic synthesis (AS) moves the creation of application engines (algorithms on silicon) to a higher level of abstraction, giving significant time and cost savings. Deploying AS for this defining part of the IC not only pays immediate benefits, but can also be the critical first step in moving the complete design process to a higher level of abstraction. Once AS is established, the methodology can be used to drive verification and validation upwards too, followed by the hardware/software hand off. Using a step-by-step approach, AS can capture the whole of the IC design, at a level of abstraction capable of quickly handling growth in complexity.

A typical IC

A complex IC for most consumer applications comprises, at the highest level, four discrete types of IP:

Application engines (video codecs, wireless modems)
Star IPs (CSU, DSP)
Connectivity and Control IP (USB, DMA)
Memory

The application engine, or algorithm in silicon, is the most critical and time-consuming part of any IC design: critical because it defines and differentiates the end product; time-consuming because the algorithms are complex, the requirements exacting in terms of power, performance and area, and the algorithm changes significantly with each revision.

Complex application engines such as those used in multimedia, imaging, wireless, security and networking domains, are traditionally designed block-by-block, either by reusing previously designed blocks, or by creating new RTL blocks manually. The immense amount of time this latter step takes can force designers to re-use blocks and IP which are not specifically targeted at the current application in order to meet budgets and deadlines, resulting in less than optimal performance.

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