Capturing and communicating power-efficient design knowledge

Using a kit-based approach as part of a complete power-efficient design solution

By Neil Hand, Director, Solutions Marketing, at Cadence Design Systems.
edadesignline.com (August 21, 2008)

In recent years, power consumption has moved to the forefront of ASIC and system-on-chip (SoC) development concerns. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Furthermore, with every new process generation, leakage power consumption increases at an exponential rate.

A wide variety of power-efficient design techniques have been developed to address the various aspects of the power problem, including the use of clock gating, multi-switching threshold (multi-Vt) transistors, multi-supply multi-voltage (MSV), substrate biasing, dynamic voltage and frequency scaling (DVFS), and power shut-off (PSO).

However, 'Low-power and Power-Efficient Design' isn't just something that can be 'bolted on' at the end of the development process. Power, timing, and area are overlapping and potentially conflicting goals that need to be balanced throughout the flow. To meet aggressive design constraints and schedules, it is no longer sufficient to consider power only in the implementation phase of the design. The size and complexity of today's ICs make it imperative to consider power throughout the complete design process, from the chip/system architectural phase; through the implementation architecture phase; through design (including micro-architecture decisions); and all the way to implementation with power-aware synthesis, placement, and routing. Similarly, to prevent functional issues from surfacing in the final silicon, power-aware verification must be performed throughout the development process including final signoff.

To address power issues, today's design environments boast a wide variety of sophisticated power-aware tools and methodologies. However, even with the high level of automation that such tools provide, applying these techniques can require substantial effort, introduce new risks, and can increase the complexity associated with design, implementation, and verification.

In order to ensure smooth adoption of power-efficient design techniques, we need a way to enable all team members regardless of power experience to utilize the capabilities at their disposal without needing to become power experts, or to learn by trial and error.

This article describes the concept of a 'low-power kit' that when applied as part of a complete power-efficient design solution enables teams with and without power expertise to adopt advanced design techniques efficiently and effectively. A low-power kit gathers expert knowledge and best practices to: eliminate common problems; establish flows to ensure tools and technologies are applied to achieve the best results; and establish processes to ensure predictability.

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