Bridging options enable FPGA-based configurable computing

By Mike Alford, Gennum Corp
EE Times (08/28/08, 06:00:00 PM EDT)

As PCI Express continues to invade embedded systems, the history of legacy PCI is repeating itself. The twist is that FPGAs have taken on processing tasks within many embedded systems, augmenting or displacing dedicated processors and DSPs. Consequently, FPGA endpoint bridging solutions for PCIe must enable the FPGAs to truly fulfill their new role.

For common PC applications, such as gigabit Ethernet, RAID/SATA, 3-D graphics accelerators and so on, there are cost-effective, off-the-shelf ASIC solutions. However, when dedicated solutions aren't available, the choices are less clear. The solutions available include:

Custom ASIC: For cost and time-to-market reasons, this solution is out of reach except in applications that ship in very high volume.
Legacy bridge: This option provides quick time-to-market by simply attaching a PCIe-to-PCI bridge to an existing legacy PCI design. However, the legacy PCI bus becomes a bottleneck. For cost-sensitive applications, the legacy bridge is an extra burden. If performance is not as important, this option may be acceptable.
FPGA: Implementing PCIe in an FPGA requires high-speed SerDes capability, which can be expensive. Also, the FPGA option is a time-consuming endeavor requiring the system designer to purchase IP, integrate the IP with the PHY and application logic, close timing in the FPGA, undertake a lengthy verification task, and compliance-test the result. Also, there are system issues to consider when using FPGAs, such as "live at power up" (more on that later) and firmware upgrade limitations.
FPGA with an external PIPE (PHY Interface for the PCIe): Using a dedicated PIPE PHY chip together with a lower cost FPGA, where the SerDes capability is not present, may provide a lower cost alternative. However, for four-lane (or larger) PCIe solutions, the pin count of a PIPE PHY is significant. This, in combination with the relatively large transaction/link layer IP required for even basic operation excludes the smaller low-cost devices. Also, the PIPE PHY solution doesn't solve any of the lengthy development cycle issues associated with PCIe.
Application-specific standard products: ASSPs, such as the Gennum GN4124 local-bus endpoint bridge, can provide all of the PCIe endpoint functions (PHY, link layer, transaction layer and so on.) to enable a simple interface to a custom endpoint application. The GN4124 is similar to the conventional local bus bridges that eased the implementation of the original PCI bus in embedded systems.