Building a configurable embedded processor - From Impulse C to FPGA

By combining Xilinx FPGAs and Impulse's EDA tools with a bit of ingenuity, embedded designers can extend the instruction set of the processors running in the FPGAs to add their own functions to a design.

By David Pellerin, Impulse Accelerated Technologies and Dan Isaacs, Xilinx
pldesignline.com (September 09, 2008)

When most design groups think of the term "configurable processing," their minds immediately go to configurable processors offered by IP vendors. But those designers may be overlooking an obvious and trusted alternative: processor- laden FPGAs. Today FPGA vendors offer high performance industry standard MPU cores on board feature-rich FPGAs.

By using a mix of FPGA vendor and EDA vendor tools and a bit of ingenuity, embedded designers can extend the instruction set of the processors running in these FPGAs to add their own unique functions to their designs. And they can do so without having to go back to school to get a degree in hardware engineering.

Over the last couple of years, FPGA and EDA vendors have made great strides in creating software-to-FPGA tools that will allow embedded designers to effectively use FPGAs to increase the performance of their designs, while meeting timing budgets and cutting bill of material costs.

Let's examine a configurable FPGA-based hardware accelerator methodology in which we'll use an auxiliary processing unit (APU) controller interface to integrate co-processing accelerators to vastly speed up a system's overall performance.

In particular, we'll employ this configurable FPGA-based hardware accelerator methodology to increase the performance of a machine vision system that formerly employed an embedded processor.

Traditionally, an application such as a machine vision system requires a substantial amount of computation, far more than what a single processor can handle. Because a single processor isn't a viable alternative, some design groups may consider using one or more higher-end DSP devices.

But increasingly designers are employing a hardware-accelerated approach using an FPGA, in which designers can implement part of the application as software running on an embedded processor (or multiple embedded processors) within the FPGA, while they implement performance-critical portions of the application, such as video image filtering, as hardware accelerators within that same FPGA.

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