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Tutorial: The Role of JTAG in system debug & test throughout the embedded system development lifecycle
By Lyle Pittroff, Mentor Graphics
Embedded.com (10/22/08, 03:00:00 AM EDT)
With each turn of Moore's Law, designers at every phase in the development process are challenged with new levels of complexity. Chip designers must not only get the integrated circuit (IC) logic, performance, power and yield right on first silicon.
In addition, system developers must extend that first time success to the board-level reference design, boot code, operating system (OS) port and application software, not to mention flash programming, manufacturing test methods, and field support. Meanwhile, meeting tight deadlines and cost objectives have never been more challenging.
Changing Bottlenecks
As the technologies of hardware and software development have evolved, so has the nature of system test and debug. Not only has Moore's Law impacted processor and memory design, but analogous changes have also taken place in integrating system functionality, the integration of operating systems (or real time operating systems (RTOS)) into embedded systems, and the amount of applications software bundled into the end product.
Let's roll the clock back. In the days of large scale integration (LSI) components (at least 1000 gates) the central processing unit (CPU) was only the CPU, bound by the limits of the semiconductor process technology, power consumption and yield available at that time.
Debugging was largely confined only to the process of integrating hardware functions, adjusting inter-chip timing and verifying logic functionality. System software was on the order of hundreds of kilobytes and limited by how much code would fit within the budgeted memory space.
How times have changed. Today, both memory space and high CPU clock frequencies are "almost free." The design, debug and test challenge has evolved from hardware component integration and debug to high-level simulation of the system hardware design prior SOC tape-out, before moving on to system software modeling, and then on to integration of hundreds of megabytes (MB) of system software.
At system level, most of today's embedded devices require full-featured embedded operating systems running multiple application programs managed with memory management units (MMUs), and increasingly also provide some sort of networking capabilities such as local area networks (LANs) or wireless network connectivity for control or network access to databases or voice, data and video services.
At the heart of contemporary embedded solutions are systems on chip (SOCs) with millions of gates, integrating cache, scratchpad random access memory (RAM), and peripheral functions onto one chip; many component interfaces are buried within the chip and no longer available at the pin or board level for system test/debug. The CPU core is now running at hundreds of megahertz (MHz), and has integrated many of the hardware interfaces, so historical test methodology is no longer possible.
Embedded.com (10/22/08, 03:00:00 AM EDT)
With each turn of Moore's Law, designers at every phase in the development process are challenged with new levels of complexity. Chip designers must not only get the integrated circuit (IC) logic, performance, power and yield right on first silicon.
In addition, system developers must extend that first time success to the board-level reference design, boot code, operating system (OS) port and application software, not to mention flash programming, manufacturing test methods, and field support. Meanwhile, meeting tight deadlines and cost objectives have never been more challenging.
Changing Bottlenecks
As the technologies of hardware and software development have evolved, so has the nature of system test and debug. Not only has Moore's Law impacted processor and memory design, but analogous changes have also taken place in integrating system functionality, the integration of operating systems (or real time operating systems (RTOS)) into embedded systems, and the amount of applications software bundled into the end product.
Let's roll the clock back. In the days of large scale integration (LSI) components (at least 1000 gates) the central processing unit (CPU) was only the CPU, bound by the limits of the semiconductor process technology, power consumption and yield available at that time.
Debugging was largely confined only to the process of integrating hardware functions, adjusting inter-chip timing and verifying logic functionality. System software was on the order of hundreds of kilobytes and limited by how much code would fit within the budgeted memory space.
How times have changed. Today, both memory space and high CPU clock frequencies are "almost free." The design, debug and test challenge has evolved from hardware component integration and debug to high-level simulation of the system hardware design prior SOC tape-out, before moving on to system software modeling, and then on to integration of hundreds of megabytes (MB) of system software.
At system level, most of today's embedded devices require full-featured embedded operating systems running multiple application programs managed with memory management units (MMUs), and increasingly also provide some sort of networking capabilities such as local area networks (LANs) or wireless network connectivity for control or network access to databases or voice, data and video services.
At the heart of contemporary embedded solutions are systems on chip (SOCs) with millions of gates, integrating cache, scratchpad random access memory (RAM), and peripheral functions onto one chip; many component interfaces are buried within the chip and no longer available at the pin or board level for system test/debug. The CPU core is now running at hundreds of megahertz (MHz), and has integrated many of the hardware interfaces, so historical test methodology is no longer possible.
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