English
Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 2
By Scott Schaefer, Micron Technology
Embedded.com (11/25/08, 03:40:00 PM EST)
DDR2/DDR3 Functionality
Up to this point, the discussion started in Part 1 has focused on clock jitter in terms of a DRAM's functionality as opposed to it working correctly; there is a subtle but important difference. DDR2/DDR3 clock jitter specifications are applied to input timings only; output timings are stated without any clock jitter and any clock jitter effects must be added to them.
Suffice it to say that there is a reasonably good explanation why this became the industry-standard methodology. Thus, clock jitter analysis needs to be separated between input timings concerns (will the device function correctly?) and output timing concerns (will the data eye be big enough?)
Embedded.com (11/25/08, 03:40:00 PM EST)
DDR2/DDR3 Functionality
Up to this point, the discussion started in Part 1 has focused on clock jitter in terms of a DRAM's functionality as opposed to it working correctly; there is a subtle but important difference. DDR2/DDR3 clock jitter specifications are applied to input timings only; output timings are stated without any clock jitter and any clock jitter effects must be added to them.
Suffice it to say that there is a reasonably good explanation why this became the industry-standard methodology. Thus, clock jitter analysis needs to be separated between input timings concerns (will the device function correctly?) and output timing concerns (will the data eye be big enough?)
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 1
- Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3
- Specifying a PLL Part 2: Jitter Basics
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2
- Dealing with memory access ordering in complex embedded designs
New Articles
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
Most Popular
- System Verilog Assertions Simplified
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution