Video encoding with low-cost FPGAs for multi-channel H.264 surveillance
and Vicenzo Liguori, Director, Ocean Logic Pty Ltd.
videsignline.com (November 28, 2008)
Building a high-performance, quad-channel H.264 encoder using low-cost, low-power FPGA architecture.
Low-cost FPGAs are now making it possible to implement high- performance encoding systems on a cost-effective and low-power FPGA fabric. This enables systems with the right combination of power, performance, and price-points to be built using well understood FPGA fabric.
This article first lays out the architecture advantages of FPGAs for low-cost, yet high-performance video processing applications and then shows how these advantages translate into a real-world application in the rapidly expanding field of video surveillance systems.
Advantages of implementing video processing in low-cost FPGAs
Today's low-cost FPGAs feature a host of silicon features that enable high performance signal processing -- abundant multipliers, fast fabric performance, and large amounts of on-chip memory (see Table 1). This makes low-cost FPGAs an ideal platform to implement an emerging class of cost-sensitive, yet high quality image processing applications.
A good example is the family of Cyclone III FPGAs that are fabricated on advanced 65nm process technology and has abundant multiplier, memory, and logic resources that enable them to implement algorithmic-intensive applications such as video and image processing.
Power is an increasingly important consideration for many system designers. Built on the TSMC 65-nm low-power process technology, these FPGAs have additional silicon and software optimizations to offer an extremely low power consumption number.
E-mail This Article | Printer-Friendly Page |
|
Ocean Logic Pty Ltd Hot IP
Related Articles
- Ultra HD H.264 Video Codec IP solution on Zynq FPGA
- A configurable FPGA-based multi-channel high-definition Video Processing Platform
- H.264 "zero" latency video encoding and decoding for time-critical applications
- How to map the H.264/AVC video standard onto an FPGA fabric
- Meeting the Challenge of Real-Time Video Encoding: Migrating From H.263 to H.264
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)