PRODUCT HOW-TO: Doing embedded design with an Eclipse-based IDE
Step-by-step, Express Logic's John Carbone describes how to use the Ecipse-based BenchX Integrated Development Environment to do embedded systems design.
By John Carbone, Express Logic
Embedded.com (12/16/08, 12:30:00 AM EST)
The open-source Eclipse movement has become a major factor in the software industry largely because it offers developers a free comprehensive Integrated Development Environment (IDE) and the ability to take advantage of a large number of free or inexpensive add-in productivity tools.
Thanks to the broad provisions of the Eclipse framework, it is possible to create an optimized-for-embedded Eclipse IDE at a price point in line with the open-source philosophy.
By combining Eclipse, the GNU C/C++ toolchain, and a host-target debug probe in a complete, integrated, and commercially supported package, Express Logic has delivered BenchX, an enhanced, embedded-optimized, Eclipse-based IDE, which can be licensed for only $1,000 per developer seat.
As shown in Figure 1 below, this IDE combines an embedded optimized Eclipse IDE, GNU C/C++ compiler and toolchain, and a host-target debug probe in a complete, integrated, and commercially supported package.
Figure 1. Combining Eclipse with GNU and a host debug probe
To simplify the multiple perspectives found in Eclipse/CDT, a single "Embedded Perspective" provides all the necessary view windows relevant to embedded system development. This greatly reduces the complexity of using Eclipse for embedded systems.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Embedded flash process enhances performance: Product how-to
- PRODUCT HOW-TO: Increase embedded processor efficiency through the use of distributed processing blocks
- PRODUCT HOW-TO: The care and feeding of embedded Linux running on MIPS CPUs
- PRODUCT HOW-TO: Use ARM DBX hardware extensions to accelerate Java in space-constrained embedded apps
- FPGA constraints for the modern world: Product how-to
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)