USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
Turbo encoders boost efficiency of a femtocell's DSP
By Hazarathaiah Malepati and Yosi Stein, Analog Devices
Embedded.com (01/04/09, 11:30:00 AM EST)
Recently, the concept of small femtocell base stations has been gaining popularity in mobile applications because of their advantages over traditional macrocells in terms of coverage, compatibility, and cost.
Because of cost and performance constraints, femtocell designs must have more or less the same level of modularity and complexity as macrocells, as well as affordability, to be used by individuals rather than communities.
But to achieve signal strengths at least the equal of traditional macrocell-based systems, femtocells have to be designed with multiple channels supporting bit rates as high as 14.4 Mbps. To do this, designers face a significant challenge: encode the multichannel bit-stream on the system's digital signal processing (DSP) engine with sufficient compute headroom for the rest of the system's essential operations.
In this article, we describe how to implement a highly efficient algorithm based on turbo codes for use in a Blackfin-based 14.4 Mbps 3G femtocell design that consumes as low as 100 MIPS of the 600 available Blackfin MIPS, leaving more than enough resources for other system operations.
Turbo codes have attracted great attention in the industry and research communities since their introduction in 1993 because of their remarkable performance. The turbo codes operate near--with a signal-to-noise ratio (SNR) gap of 0.7dB or less--the ultimate limits of capacity of a communication channel set by Claude E. Shannon.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Today's DSP Design Challenge - Power Efficiency
- How to Turbo Charge Your SoC's CPU(s)
- Optimizing efficiency and flexibility in DSP systems
- DSPs with PCI Express interface extend connectivity while improving performance and power efficiency
- How throughput enhancements dramatically boost 802.11n MAC efficiency--Part II