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Innovating methodology beyond base classes
By Janick Bergeron, Synopsys Inc
edadesignline.com (January 05, 2009)
By adopting the SystemVerilog standard, the EDA and the semiconductor industry took an important step to address the verification productivity problem. SystemVerilog introduced new verification techniques such as constrained-random testbenches, functional coverage, and assertions and evolved Verilog into a unified design and verification language. SystemVerilog also introduced object-oriented programming concepts which were new to hardware engineers. To learn and adopt new techniques, given compressed project schedule, is always a challenge for the engineers. To help with this problem, Synopsys collaborated with ARM to define the VMM Methodology, four years ago. The methodology was published in the Verification Methodology Manual for SystemVerilog book. It helped engineers leverage the power of SystemVerilog concepts to create efficient and reusable verification environment. VMM delivered a set of base classes to help engineers create constrained-random transactions, define comprehensive coverage objects, use assertions effectively, collect error messages efficiently, and carry out other critical verification tasks successfully.
While base classes accelerate SystemVerilog deployment, the verification challenge continues to grow. There is a need to further advance verification productivity. Synopsys has been addressing this need by creating VMM Applications on top of the base classes. These applications allow engineers to focus on finding bugs in their designs, instead of spending time on repetitive tasks for every project. Among other tasks, the these applications address verification of registers, memory elements; data stream scoreboarding for self-checking testbenches; creation of reusable testbenches from block to chip to system-level verification; and deploying coverage-based verification planning and tracking. Recently ARM, Renesas and Synopsys announced VMM LP which expands VMM to address the emerging challenge of low power verification. VMM base classes, VMM Applications, VMM Planner specification and other VMM utilities are available for download and use at vmmcentral.org under Apache 2.0 open-source license.
edadesignline.com (January 05, 2009)
By adopting the SystemVerilog standard, the EDA and the semiconductor industry took an important step to address the verification productivity problem. SystemVerilog introduced new verification techniques such as constrained-random testbenches, functional coverage, and assertions and evolved Verilog into a unified design and verification language. SystemVerilog also introduced object-oriented programming concepts which were new to hardware engineers. To learn and adopt new techniques, given compressed project schedule, is always a challenge for the engineers. To help with this problem, Synopsys collaborated with ARM to define the VMM Methodology, four years ago. The methodology was published in the Verification Methodology Manual for SystemVerilog book. It helped engineers leverage the power of SystemVerilog concepts to create efficient and reusable verification environment. VMM delivered a set of base classes to help engineers create constrained-random transactions, define comprehensive coverage objects, use assertions effectively, collect error messages efficiently, and carry out other critical verification tasks successfully.
While base classes accelerate SystemVerilog deployment, the verification challenge continues to grow. There is a need to further advance verification productivity. Synopsys has been addressing this need by creating VMM Applications on top of the base classes. These applications allow engineers to focus on finding bugs in their designs, instead of spending time on repetitive tasks for every project. Among other tasks, the these applications address verification of registers, memory elements; data stream scoreboarding for self-checking testbenches; creation of reusable testbenches from block to chip to system-level verification; and deploying coverage-based verification planning and tracking. Recently ARM, Renesas and Synopsys announced VMM LP which expands VMM to address the emerging challenge of low power verification. VMM base classes, VMM Applications, VMM Planner specification and other VMM utilities are available for download and use at vmmcentral.org under Apache 2.0 open-source license.
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