English
How to transform video SerDes from a nightmare to a dream
National Semiconductors' video SerDes solution involves a PHY chip with an interface to low-cost FPGAs and IP to implement all of the digital functionality in programmable logic.
By Mark Sauerwald, National Semiconductor
pldesignline.com (January 14, 2009)
Many IC designers wake up at night with nightmares involving mixed-signal design. A classic example involves the design of high speed serializers and deserializers (SerDes). If a process is selected which will allow good performance on the analog sections of the design – for example phase locked loops, cable drivers, and very high speed sections – then there is invariably a compromise in cost and power when it comes to the digital section.
Meanwhile, if a process is selected with an eye to low cost and low power dissipation, then the resulting small transistors struggle to meet analog requirements. If IC designers don't do a good job of their task, then the nightmares are passed on to the equipment and system designers.
One way to avoid these nightmares is to partition the task in such a way that the bulk of the analog tasks are housed on one chip manufactured in a process optimized for analog performance. Digital functions, meanwhile, should be placed on a different piece of silicon. This is the concept behind National Semiconductor's FPGA Attach video SerDes products.
The specific SerDes parts to be designed were intended for use by the broadcast video industry. Broadcast video has very specific ways of formatting and scrambling the data prior to serialization and transmission. Although there are a limited number of data rates in common use (270 Mbps, 1.485 Gbps, and 2.97 Gbps), there is a plethora of different video formats, each with slightly different formatting requirements. To make matters worse, whenever an ASIC designer releases a chip believed to support all the formats, new formats are then added to the list.
When National's design team looked at this application, the decision was made to design a chip with all of the analog portions required to implement the physical layer (PHY), along with an interface specifically designed to work with low cost FPGAs, and then to generate IP (intellectual property) which would implement all of the digital functionality in programmable logic. When new formats were devised, they could be easily accommodated with an edit to the FPGA code. The resulting products were the LMH0340 serializer, the LMH0341 deserializer and a suite of IP.
By Mark Sauerwald, National Semiconductor
pldesignline.com (January 14, 2009)
Many IC designers wake up at night with nightmares involving mixed-signal design. A classic example involves the design of high speed serializers and deserializers (SerDes). If a process is selected which will allow good performance on the analog sections of the design – for example phase locked loops, cable drivers, and very high speed sections – then there is invariably a compromise in cost and power when it comes to the digital section.
Meanwhile, if a process is selected with an eye to low cost and low power dissipation, then the resulting small transistors struggle to meet analog requirements. If IC designers don't do a good job of their task, then the nightmares are passed on to the equipment and system designers.
One way to avoid these nightmares is to partition the task in such a way that the bulk of the analog tasks are housed on one chip manufactured in a process optimized for analog performance. Digital functions, meanwhile, should be placed on a different piece of silicon. This is the concept behind National Semiconductor's FPGA Attach video SerDes products.
The specific SerDes parts to be designed were intended for use by the broadcast video industry. Broadcast video has very specific ways of formatting and scrambling the data prior to serialization and transmission. Although there are a limited number of data rates in common use (270 Mbps, 1.485 Gbps, and 2.97 Gbps), there is a plethora of different video formats, each with slightly different formatting requirements. To make matters worse, whenever an ASIC designer releases a chip believed to support all the formats, new formats are then added to the list.
When National's design team looked at this application, the decision was made to design a chip with all of the analog portions required to implement the physical layer (PHY), along with an interface specifically designed to work with low cost FPGAs, and then to generate IP (intellectual property) which would implement all of the digital functionality in programmable logic. When new formats were devised, they could be easily accommodated with an edit to the FPGA code. The resulting products were the LMH0340 serializer, the LMH0341 deserializer and a suite of IP.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity
- How FPGAs are breathing new life into the analog video format
- SerDes chip enables integration of multiple video streams
- How to transform silicon with dynamic reconfiguration
- How to implement a high-definition video design framework for FPGAs
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Synthesis Methodology & Netlist Qualification
- Streamlining SoC Design with IDS-Integrate™