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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
SAS--SATA: What You Need to Know for 6 Gb/s and Beyond
Chris Cicchetti, Finisar
commsdesign.com (Jan 25, 2009)
The introduction of 6 Gb/s SAS-2 and SATA Gen-3 promises new levels of performance for networks. At these higher speeds, however, signal integrity becomes a significantly more important design concern for equipment designers and network engineers than it was at 3 Gb/s as tolerances drop to the point where test equipment can adversely affect signal integrity. For example, a test setup that was already at the performance edge for 3 Gb/s will cause undesirable and misleading failures at 6 Gb/s.
Apart from strictly adhering to each standard's specifications, the key behind successful SAS/SATA product development and network debugging will be an understanding of the tighter tolerances at 6 Gb/s and the simple steps that one can take to minimize the impact of test equipment on the device under test. By understanding how attenuation and jitter impact signal integrity, developers and systems engineers can adjust test setups to minimize their impact during testing.
commsdesign.com (Jan 25, 2009)
The introduction of 6 Gb/s SAS-2 and SATA Gen-3 promises new levels of performance for networks. At these higher speeds, however, signal integrity becomes a significantly more important design concern for equipment designers and network engineers than it was at 3 Gb/s as tolerances drop to the point where test equipment can adversely affect signal integrity. For example, a test setup that was already at the performance edge for 3 Gb/s will cause undesirable and misleading failures at 6 Gb/s.
Apart from strictly adhering to each standard's specifications, the key behind successful SAS/SATA product development and network debugging will be an understanding of the tighter tolerances at 6 Gb/s and the simple steps that one can take to minimize the impact of test equipment on the device under test. By understanding how attenuation and jitter impact signal integrity, developers and systems engineers can adjust test setups to minimize their impact during testing.
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