English
Viewpoint: More to IP reuse than software tweaks
Mike Meredith, Forte Design Systems
EE Times (02/25/2009 11:50 AM EST)
As long as the process technologists continue to make it practical to deploy an increasing number of gates, creative design engineers will find ambitious new ways to use those gates to build competitive advantage.
Platform-based design with heavy IP reuse will continue to proliferate as more functionality is included into tomorrow's chip, but differentiation through software alone falls short of power and performance requirements.
Leading edge semiconductor and consumer products companies will continue to differentiate their products beyond IP reuse with proprietary functionality implemented in hardware. In order to maintain their competitive edge, they increasingly turn to higher levels of abstraction and synthesis for creating these proprietary hardware blocks.
While it is certainly true that platform-based design and IP reuse reduces effort compared to creating new hardware in RTL, assembling existing IP blocks is not a complete strategy for creating new SoCs comprising tens of millions of gates. Ways to create custom hardware more efficiently than handwriting RTL are also needed.
EE Times (02/25/2009 11:50 AM EST)
As long as the process technologists continue to make it practical to deploy an increasing number of gates, creative design engineers will find ambitious new ways to use those gates to build competitive advantage.
Platform-based design with heavy IP reuse will continue to proliferate as more functionality is included into tomorrow's chip, but differentiation through software alone falls short of power and performance requirements.
Leading edge semiconductor and consumer products companies will continue to differentiate their products beyond IP reuse with proprietary functionality implemented in hardware. In order to maintain their competitive edge, they increasingly turn to higher levels of abstraction and synthesis for creating these proprietary hardware blocks.
While it is certainly true that platform-based design and IP reuse reduces effort compared to creating new hardware in RTL, assembling existing IP blocks is not a complete strategy for creating new SoCs comprising tens of millions of gates. Ways to create custom hardware more efficiently than handwriting RTL are also needed.
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