7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
PCI Express Gen 3 Simplified
Embedded.com (02/24/09, 12:30:00 AM EST)
The PCI-SIG, an industry organization dedicated to developing and enhancing PCI/PCI Express (PCIe) technology, has successfully developed the PCI, PCI-X and PCIe Gen 1 and Gen 2 interconnect protocols and promoted the deployment of these technologies since PCI's inception in 1992.
In early 2008, the PCI-SIG announced the establishment of a workgroup chartered with the development of the next generation of PCIe " the PCI Express Base Specification 3.0, or PCIe Gen 3.
The Gen 3 specification is yet another step forward in enhancing the usefulness of the PCIe protocol by doubling the effective bandwidth and adding protocol enhancements to increase end-system performance.
Leading up to this development, IBM and Intel in 2006 launched an initiative called Geneseo, proposing extensions to the PCIe protocol for high-performance computing and visual processing.
Recommendations from this initiative were provided to the PCI-SIG as potential PCIe protocol enhancements. In addition to the adoption of Geneseo, several other engineering change notices (ECNs) were released by the PCI-SIG, providing enhancements for the efficiency and usefulness of the PCIe protocol.
This article will shed light on the PCIe Gen 3 standard, as well as some of the key enhancements that will be implemented in PCIe Gen 3 components.
Ten key enhancements have been completed and will be implemented in next-generation PCIe devices and systems. Some of these enhancements may get implemented into PCIe Gen 2 devices, while others will only be supported in Gen 3 products. Let's take a closer look at some of these enhancements (Table 1) approved as ECNs to the PCIe specification.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow