English
M-LVDS for true multipoint interfaces on busses--and more
By David Mulcahy, Texas Instruments
Planet Analog (Mar 30, 2009)
Over the years, various technologies have been used to transmit signals over backplane busses. As speeds increase to cater to the ever-growing volume of telecom and datacom traffic, the limitation of the older, single-ended and emitter-coupled logic techniques becomes apparent.
Multipoint, low-voltage differential signaling (M-LVDS) is an interface standard similar to LVDS. It provides the benefits of high-speed, low-power, and low-EMI transmission solutions to today's bus applications. M-LVDS is suitable for data, control, synchronization and clock signals.
In today's backplanes, high-speed signals carrying the payload data are typically point-to-point (one driver and one receiver) interfaces. These connect various core chips such as ASICs, FPGAs, DSPs, and similar. Properly terminated point-to-point interfaces offer the best performance for high-speed signals. Signaling levels used can be PECL, CML, VML and LVDS with speeds going up to 4Gbps and higher, Figure 1.
Planet Analog (Mar 30, 2009)
Over the years, various technologies have been used to transmit signals over backplane busses. As speeds increase to cater to the ever-growing volume of telecom and datacom traffic, the limitation of the older, single-ended and emitter-coupled logic techniques becomes apparent.
Multipoint, low-voltage differential signaling (M-LVDS) is an interface standard similar to LVDS. It provides the benefits of high-speed, low-power, and low-EMI transmission solutions to today's bus applications. M-LVDS is suitable for data, control, synchronization and clock signals.
In today's backplanes, high-speed signals carrying the payload data are typically point-to-point (one driver and one receiver) interfaces. These connect various core chips such as ASICs, FPGAs, DSPs, and similar. Properly terminated point-to-point interfaces offer the best performance for high-speed signals. Signaling levels used can be PECL, CML, VML and LVDS with speeds going up to 4Gbps and higher, Figure 1.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Integration of power:communication interfaces in smart true wireless headset designs
- What is JESD204C? A quick glance at the standard
- Why Interlaken is a great choice for architecting chip to chip communications in AI chips
- Automotive electronics revolution requires faster, smarter interfaces
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology