English
Using an interface wrapper module to simplify implementing PCIe on FPGAs
By Stephane Hauradou, PLDA
Embedded.com (04/07/09, 02:29:00 AM EDT)
Many end-applications today use an FPGA-based design as an inherent component of their solution. They often require PCI Express (PCIe) as an indispensible feature, to provide a standardized interface with other components in the system.
Historically, PCI Express has been difficult to implement in FPGA because it requires multi-gigabit SerDes and analog circuitry with stringent electrical requirements.
Additionally, PCI Express implementations requires complex digital logic including Physical, Data Link and Transaction layers with large data paths running at high frequency, thus making it difficult to implement in FPGA.
The most common methods used for implementing PCI Express in FPGAs include:
Figure 1 - ASSP/PCIe Bridge Chip
Embedded.com (04/07/09, 02:29:00 AM EDT)
Many end-applications today use an FPGA-based design as an inherent component of their solution. They often require PCI Express (PCIe) as an indispensible feature, to provide a standardized interface with other components in the system.
Historically, PCI Express has been difficult to implement in FPGA because it requires multi-gigabit SerDes and analog circuitry with stringent electrical requirements.
Additionally, PCI Express implementations requires complex digital logic including Physical, Data Link and Transaction layers with large data paths running at high frequency, thus making it difficult to implement in FPGA.
The most common methods used for implementing PCI Express in FPGAs include:
- ASSP/PCI Express Bridge chip
- FPGA with digital controller soft-IP and built-in SerDes/PHY
- FPGA with digital controller soft-IP and external discrete PHY chip
- FPGA with built-in PCI Express hard-IP
Figure 1 - ASSP/PCIe Bridge Chip
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)
- Implementing PCI Express Designs using FPGAs
- DSPs with PCI Express interface extend connectivity while improving performance and power efficiency
- Test tools to empower engineers for PCIe 3.0 designs
- Implementing LTE on FPGAs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)