English
55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Viewpoint: Opportunity to win on different design fronts
By Ken Chen, TSMC
powermanagementdesignline.com (June 12, 2009)
Beyond pure process scaling which is necessary to meet today's price, power, and performance goals, chip designers have to grapple with tighter integration and product performance specialities in areas such as integrated power management, image sensing, application-specific data conversion, and enhanced display drivers.
These broader aspects of semiconductor process development may not grab the headlines as often but they are no less important to the long-term success of final products in the market.
When we talk about integration we automatically include computational performance — signal processing and microcontrollers. However the other design fronts I'm also passionate about are the physical interfaces such as sensing, actuating and application-specific drive signals which allow every designer to give an SoC device his competitive edge, his speciality.
powermanagementdesignline.com (June 12, 2009)
Beyond pure process scaling which is necessary to meet today's price, power, and performance goals, chip designers have to grapple with tighter integration and product performance specialities in areas such as integrated power management, image sensing, application-specific data conversion, and enhanced display drivers.
These broader aspects of semiconductor process development may not grab the headlines as often but they are no less important to the long-term success of final products in the market.
When we talk about integration we automatically include computational performance — signal processing and microcontrollers. However the other design fronts I'm also passionate about are the physical interfaces such as sensing, actuating and application-specific drive signals which allow every designer to give an SoC device his competitive edge, his speciality.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Calibrate and Configure your Power Management IC with NVM IP
- How NoCs ace power management and functional safety in SoCs
- Analog and Power Management Trends in ASIC and SoC Designs
- Breaking new energy efficiency records with advanced power management platform
- New Power Management IP Solution Can Dramatically Increase SoC Energy Efficiency
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone