Securing SoC Platform Oriented Architectures with a hardware Root of Trust
By Craig Rawlings, Certicom Corp.
Embedded.com (July 06, 2009)
While it has long been the purview of electronic product vendors to rise to the challenges of managing ever shortening product life cycles, a new trend is afoot that may turn the tables in favor of longer platform hardware life cycles.
As embedded programmable processor based features increase in power, increasingly sophisticated platform System on Chip (SoC) architectures, including configurable hardware, boot code, firmware, and system software now bring to systems the ability to modify basic hardware functions and features without redesigning the SoC from scratch.
The real trick is how to efficiently and securely manage these changes to system hardware throughout the supply chain. For conceptually newer products there will be requirements that drive configuration of in-market system features. In other words, the customer may have the ability in the future to upgrade his product with premium system features after his or her original purchase.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Why Hardware Root of Trust Needs Anti-Tampering Design
- Securing the IoT: Part 2 - Secure boot as root of trust
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Add Security And Supply Chain Trust To Your ASIC Or SoC With eFPGAs
- Securing the IC Supply Chain - Integrating PUF-Based hardware security
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study