Virtual testing with model-based design
industrialcontroldesignline.com (August 17, 2009)
Virtual testing, based on system simulation and Model-Based Design, takes the traditional "test-at-the-end" system development process (represented in the V diagram) and makes it more iterative. Virtual testing shortens both the design cycle and the final physical testing phase.
The Problems: System Complexity and Late-Stage Error Detection
Complexity in embedded software development is driving the cost of test and verification to as much as 70% of overall development costs. Industrial automation, automotive, and aerospace engineers conduct exhaustive design and code reviews and build increasingly complex test systems to confirm that the software in embedded processors meets high-integrity standards and design requirements. And as verification consumes more time, engineers have fewer opportunities to innovate and create product differentiation through design optimization.
Many organizations are finding that most errors they uncover in test and integration were introduced at the beginning of the design process while interpreting system requirements. Engineers now face the challenge of checking for errors and "cleaning them out" closer to the beginning of the development process, when they are cheaper to fix.
Finally, as development teams grow and become geographically dispersed, they are seeking better ways to collaborate.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Dealing with automotive software complexity with virtual prototyping - Part 3: Embedded software testing
- Using model-based design to test auto embedded software
- Model-based approach allows design for yield
- Exploring Machine Learning testing and its tools and frameworks
- QA Automation Testing with Container and Jenkins CICD
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)