Evaluating the performance of multi-core processors - Part 2
By Max Domeika, Intel
Embedded.com (09/16/09, 12:03:00 PM EDT)
One common question when customers review data from microprocessor benchmarks such as those discussed in Part 1 is "How well will benchmark performance predict my particular application's performance if I employ your new processor or new compiler?"
In other words, if a new processor or different compiler increases the performance of benchmark X by Y%, how much will the processor or compiler benefit my application?
Of course, the answer is: it depends. Your application is not exactly like the benchmark program, and while the processor architects and compiler engineers may use the benchmark to assess the performance of features they are adding during development, they do not necessarily have access to or tune specifically for your application.
Therefore, you should be skeptical if someone claims that you will see the same performance benefit from using a new processor or compiler as what is shown from the benchmark data.
That said, you should expect some performance improvement and there are a couple of statistical techniques that can be employed to help improve the degree of confidence you have in benchmark data in estimating your end application performance.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Evaluating the performance of multi-core processors - Part 1
- Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device
- Using sub-RISC processors in next generation customizable multi-core designs: Part 1
- Techniques for debugging an asymmetric multi-core application: Part 2
- Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)