English
Viewpoint: Solving the nanoscale IC design paradox
By Phil Bishop, CEO, Pyxis Technology, Inc.
edadesignline.com (October 14, 2009)
There is a paradox brewing in the layout of integrated circuit designs at nanometer nodes. IC design teams are choosing between layout automation vs. full custom design techniques.
While the automated layout tools seem fast, engineers may grow old fixing timing, power and yield problems on the back end of the flow. Meanwhile, full custom tools give designers more control over custom digital and mixed-signal circuit layouts, but the lack of automation can make project completion seem light-years away.
The nanoscale IC design paradox is that designers need both hands-on custom control and high-speed automation performance.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Reliability challenges in 3D IC semiconductor design
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
- Calibrate and Configure your Power Management IC with NVM IP
- IC design: A short primer on the formal methods-based verification
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study