English
FPGA-based rapid prototyping of ASIC, ASSP, and SoC designs
By Juergen Jaeger, Synopsys Inc.
pldesignline.com (October 21, 2009)
ASIC designs continue to increase in size, complexity, and cost (for the purpose of these discussions, the term ASIC is assumed to encompass ASSP and SoC devices). At the same time, aggressive competition makes today's electronics markets extremely sensitive to time-to-market pressures. Furthermore, market windows are continually narrowing; in the case of consumer markets, for example, a "typical" ASIC design cycle is in the order of 9 to 18 months, while the window of opportunity for the introduction of a product using this device can be as little as 2 to 4 months.
Failing to have a product available at the beginning of the intended market window may result in significantly reduced revenue (or a complete loss of revenue and investment if the window is missed in its entirety). These factors have dramatically increased the pressure for ASIC designs to be "right-first-time" with no re-spins. In turn, this has driven the demand for fast, efficient, and cost-effective verification at both the chip and system levels.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- How to improve FPGA-based ASIC prototyping with SystemVerilog
- Analog and Power Management Trends in ASIC and SoC Designs
- Custom Corner Characterization for Optimal ASIC/SoC Designs
- 10 Favorite FPGA-Based Prototyping Boards
- Timing-Driven Hybrid RTL/Gate Partitioning for Predictable FPGA-Based Prototyping