Executive Opinion: Successful Memory IP Development Depends on GEP

Update: Synopsys Expands DesignWare IP Portfolio with Acquisition of Sidense Corporation (Oct. 17, 2017)

Through years of experience, people develop ‘their’ ways of doing things. With time they become ‘their own’ best engineering practices. Some of these are captured in writing and become part of a Good Engineering Practice (GEP). Some never leave the stage of ‘my’ best engineering practice.

By the nature of things, startups tend to be less formal. Processes, methodologies, and check-off lists are introduced as the company matures and its customer base grows. It is quite likely that a fair amount of GEP originated from live experiences, good or bad.

It is hard to argue that a good, detailed specification is one of the most important pieces of a GEP. Whether it is an external specification or a description to be used between functional groups in the organization, a good spec will directly impact whether the project or product is done on time, effectively, and will meet customer/company expectations, or it will lead to costly schedule overruns, missed delivery dates, and repeated silicon runs.

Memory is quite unique amongst silicon IP. The number of possible memory configurations makes it almost impossible to simulate and characterize all of them. Each memory company develops its own way of dealing with this challenge. Some use tools and brute force and computational power of modern computers, while others develop sophisticated circuit optimization and minimization techniques. Either way, a tested, proven, accurate and a fast methodology to simulate any memory configuration is a key component of GEP.

Close cooperation of circuit and layout engineers is critical for area-efficient designs. It is not far from the truth that layout is leading the design effort. Quite frequently circuit solutions are dictated by layout constraints.

Good simulation techniques and thorough circuit and layout reviews, along with functional verification with comprehensive test benches should yield working and well performing IP but nothing replaces a test chip. Having the IP manufactured at least once will provide a lot of insight into how a memory macro will work in customer applications. Corner lots provide even more valuable information about operating ranges and available margins. Obviously the most detailed testing will not help if the results are not fed back to the design group.

All what has been mentioned so far is quite generic and broad. These fundamental pieces of a GEP have to be supported by many ‘smaller ticket’ items such as good project documentation, a clean and easy to understand set of schematics, a design changes tracking system and… it never hurts to work with a team of engineers with their own good engineering habits.