English
Process Detector (For DVFS and monitoring process variation)
Viewpoint: Need to move beyond the network-on-chip
Ray Brinks, Vice President, Engineering, Sonics, Inc.
EE Times (01/04/2010 2:49 PM EST)
Over the last decade, designers have been content with standard connectivity methodologies to fulfill the needs of their system-on-chip (SoC) designs.
With today's design starts using 65nm design rules or smaller, the number of cores in an SoC can exceed 100. Connecting 50 or 100 cores breeds challenges that SoC design teams did not have to previously face.
The inherent communications between on-chip cores is now taking on more of the comprehensive characteristics of a network rather than simply a bus. These characteristics include standard interface protocols, sockets at the edge of the network to allow cores to maintain a level of independence, and scalability so that the network can grow or shrink as needed. Enter the network-on-chip (NoC).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow