English
Viewpoint: Need to move beyond the network-on-chip
Ray Brinks, Vice President, Engineering, Sonics, Inc.
EE Times (01/04/2010 2:49 PM EST)
Over the last decade, designers have been content with standard connectivity methodologies to fulfill the needs of their system-on-chip (SoC) designs.
With today's design starts using 65nm design rules or smaller, the number of cores in an SoC can exceed 100. Connecting 50 or 100 cores breeds challenges that SoC design teams did not have to previously face.
The inherent communications between on-chip cores is now taking on more of the comprehensive characteristics of a network rather than simply a bus. These characteristics include standard interface protocols, sockets at the edge of the network to allow cores to maintain a level of independence, and scalability so that the network can grow or shrink as needed. Enter the network-on-chip (NoC).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology