English
Bluetooth low energy v6.0 Baseband Controller, Protocol Software Stack and Profiles IP
A real solution for mixed signal SoC verification
Intrinsix
edadesignline.com (January 07, 2010)
Introduction
As more complex, mixed signal System on Chip (SoC) designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed signal verification presents a unique challenge as the analog portion of the design requires highly accurate, and time consuming, analog simulation (Spice for example).
Furthermore, without a digital representation of the analog design, full digital regression simulations are not possible for the SoC. This is insufficient for verifying connectivity and basic functionality of the integrated SoC at the system level. Intrinsix recently evaluated the Cadence Design Systems' Real Number Modeling (RNM) methodology as a possible solution for achieving efficient mixed signal verification.
Intrinsix is a leading supplier of sigma-delta data converter IP. Many of our customers are using Sigma-Delta Modulator (SDM) technology to develop sensors for automotive, consumer and aerospace applications. All of these designs require similar signal processing.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- SoC Test and Verification -> Testing mixed-signal Bluetooth designs
- Ins and Outs of Assertion in Mixed Signal Verification
- Modeling and Verification of Mixed Signal IP using SystemVerilog in Virtuoso and NCsim
- Mixed Signal Design & Verification Methodology for Complex SoCs
- Analog Mixed Signal Verification Methodology (AMSVM)
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology