Power Supply Design Considerations for Modern FPGAs
By Dennis Hudgins, National Semiconductor
powermanagementdesignline.com (January 06, 2010)
Introduction
Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, power on, and soft-start requirements, can result in unreliable power up or potential damage to the FPGA.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- CPU Soft IP for FPGAs Delivers HDL Optimization and Supply Chain Integrity
- Protecting FPGAs from power analysis security vulnerabilities
- Enable low power design with FPGAs
- Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems
- Power considerations in designing with 90 nm FPGAs
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design