English
Power Supply Design Considerations for Modern FPGAs
By Dennis Hudgins, National Semiconductor
powermanagementdesignline.com (January 06, 2010)
Introduction
Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, power on, and soft-start requirements, can result in unreliable power up or potential damage to the FPGA.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- CPU Soft IP for FPGAs Delivers HDL Optimization and Supply Chain Integrity
- Protecting FPGAs from power analysis security vulnerabilities
- Enable low power design with FPGAs
- Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems
- Power considerations in designing with 90 nm FPGAs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)