Panel finds many ways to build a platform

Panel finds many ways to build a platform
By Ron Wilson, EE Times
February 1, 2002 (2:55 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020130S0057

SANTA CLARA, Calif. — The meaning and usefulness of platform-based design were discussed in a panel session Tuesday (Jan. 29) at DesignCon.

Grant Martin, a Cadence Design Systems Inc. fellow and author of a book on the subject, began the discussion by defining the word "platform" as it is used in systems design. Waxing mathematical, he defined the term as "a coordinated family of architectures heavily constrained so as to promote design reuse." The term could also be quite relative, he warned: one person's project was another person's platform, and the word can mean quite different things to hardware and software engineers on the same project.

But Martin did offer concrete examples, suggesting three categories of platforms. There are, he said, application-focused platforms, such as reference designs for Bluetooth. There are CPU-focused platforms, such as some of the collections of processor, bus and peripheral intellectual property (IP) and software provided by ARM Ltd. And there are communications-based platforms, where the essence of the product is the mechanism for communicating between IP blocks, such as the Sonics Inc. product.

Kathleen McGroddy, a senior manager at IBM Corp., said her organization had followed a clear evolutionary path. "IBM started with a communications-centric approach, and then moved to CPU-centric platforms based on our PowerPC core," she said. "Now we are evolving toward application-specific platforms." McGroddy added that much more went into a platform than just blocks of hardware IP. Inserting chip-level timing assertions into the IP had become vital to rapid development, she said, along with developing a C-language verification environment for the platforms.

Victor Berman, director of marketing at Improv Systems Inc., took quite a different view of platforms. He explained Improv's approach for mapping an abstractly-described application onto a flexible collection of processing engines and automatically generating the mapping, code and even test sequences. This process required considerable applications knowledge, he asserted.

Finally, Zvi Or-Bach, president and chief executive officer of e-ASIC Corp., outlined yet a third approach to a platform: a fabric of configurable logic cells embedded in a segmented array of interconnect. The logic cells, Or-Bach said, are programmed via bit streams, the same as FPGA logic cells. Each can be configured as a logic function, a programmable logic cell or an SRAM. But the interconnect is configured with a single metal mask, which can be used to make connections on four metal layers. The resulting device can be, for example, fabricated in a 130-nm CMOS process along with a CPU, bus and bulk memory, to provide standard-cell like flexibility and performance in implementing coprocessors and peripherals.

Ron Wilson is editorial director of Integrated System Design, a sister publication of EE Times.

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