Intellectual property adolescence

Intellectual property adolescence
By Ron Wilson, EE Times
December 27, 2001 (11:58 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011221S0029

Both the natural process of maturity and new pressures are changing the intellectual property industry. Every aspect, from the way IP is delivered to how it is tailored to a particular application and how it is integrated into the customer's design flow, is changing rapidly as IP, stripped of its early hope of being a growth industry, settles down to the hard work of meeting customer needs.

Delivery is an example of these changes. Traditionally, CPU cores have been hard-delivered as placed and routed cells while most other cores have been soft-supplied as synthesizable Verilog or VHDL. That is changing.

"We are seeing firm cores becoming a staple for our customers as demands for performance increase," said Dennis Kish, vice president of marketing at Actel Corp. (Sunnyvale, Calif.). In the ASIC space as well, vendors report t hat performance and process complexity are increasing the demand for hard cores and reducing interest in synthesizable IP.

Licensing a hard core simplifies the customer's design flow. But it raises some real issues if the core as supplied doesn't exactly fit the design's requirements. There are several strategies to tailoring IP to a specific application. One, championed by ARM Ltd. and MIPS Technologies Inc., is to design a core so clean and fast that most users will be able to leave it alone. This strategy can be stretched a bit by offering either instruction set extensions, such as the MIPS graphics or media extensions, or a finely tuned coprocessor interface, such as that offered by ARM. The emphasis is on keeping the processor clean and verifiable, and depending on speed to get the application done.

Another alternative, championed by the ARC Cores Inc. and Tensilica Inc. approaches, is to offer limited configurability of the core through vendor-provided tools. This can take several flavors. ARC lets users change ALU widths, addressing modes and the like, where Tensilica goes in more for adding specialized instructions. But both constrain the user's interaction with the core via rigorous tools, in order to have some control over resulting performance and verifiability.

In other areas the problem is less solvable. High-speed interfaces, analog and mixed-signal circuits are inherently delicate: even small changes mean a new design. And these vendors tend to modify the cores only in joint development with their customers. In the memory area, where not only cell-based hard designs but even custom cells may be involved, demanding designs can turn into a three-way partnership among IP vendor, customer and foundry.

Growing complexity
When the design team members are licensing IP that they don't completely understand, there is a tendency to ask for a complete solution rather than a difficult component. "These days, customers don't want just blocks of RAM; they want whole memory systems," observed Vincent Ratford, vice president of marketing at Virage Logic (Fremont, Calif.). "They may want the placement and routing of hard blocks of memory array, sense amps and control logic to be taken care of within the compiler, not left to them. We try to hand them a functioning memory subsystem that will only require a couple of thousand lines of code to hook up to the rest of the chip."

For CPU core vendors, this trend is spreading beyond the core itself. ARM, of course, has been famous for providing almost a turnkey application package including CPU, caches, bus architecture, peripheral blocks and drivers, and often legacy application software as well, for certain markets. Increasingly, processor core vendors, including such diverse architectures as MIPS and TriMedia, talk about application platforms now, rather than CPU feeds and speeds. ARC CEO John Stockton explained, "What customers want these days is a solution, not just a really hot core design. We are finding that the RTL matters less and less, and what matters is your expertise in an application — your ability to aggregate software and verification tools with the hardware and solve a problem."

The verification issue looms large here. If, as is often said, verification can be upward of 70 per cent of the design job, then it should also be a dominant consideration in selecting IP. "Verification is the real value," said MIPS chairman and CEO John Bourgoin. "A lot of the engineers we work with at clients have written CPU core designs in school. But being able to verify a design in a particular environment — that doesn't come through cores or tools, it comes through wise people bringing their experience to the relationship between core vendor and user."

Doing the integration
Integrating the core into the design flow was one of the first problems to be recognized by the industry. The initial response was to set up an industry consortium, the Virtual Socket Initiative, to create a set of standards for making IP genuine ly reusable. Toward the end of 2001, the group began quietly reporting that its work was done. There is now an openly available body of, if not standards, at least guidelines that can make IP highly reusable.

But guidelines aren't laws. In the wake of VSIA's work, a number of different responses have sprung up. One has been the creation of internal work rules by large organizations to govern their own internal IP. Another has been the creation of commercial organizations, frequently based on a particular integration architecture or tool set, that undertake to solve their customers' integration problems. The recently announced Open Core Protocol International organization, based on an integration methodology from Sonics Inc., is one such example.

A trend that may prove more influential in the future is for vendors to develop more formal working relationships between themselves, without the intermediation of a standards body or commercial integration vendor. Lisa Lipscomb , vice president of marketing at Nurlogic Design (San Diego, Calif.), said, "With complexity of the functions going up, but also with timing closure, signal integrity and skew issues getting so complex, there's a trend to encapsulate all the difficult nets inside the IP, even if that means considerably enlarging the scope of the core. For instance, an interface core these days may have not only the high-speed transceivers, but the Serdes and clock circuits all in one hardened design. "But that means one core may contain IP from several sources. So we find ourselves working with other, even sometimes competitive, IP vendors to create blocks that our customers can integrate without huge difficulties."

And that may be the best pointer to the future of IP. Instead of finding magic bullets in the standards or tool worlds to make IP blocks more usable, vendors are increasing the functionality of the blocks to encapsulate the hard parts, leaving only a relatively simple interface, a clearly defined methodology for customization, and a pack aged verification flow that encapsulates not only what the vendor knows about the implementation, but what he has learned about the application space as well. IP is becoming a way of delivering applications expertise.

References:
A directory to the VSI specifications
A datasheet describing the Open Core Protocol
A look at peripherals for ARM
Software libs for an IP core
Complete memory subsystem
Verification of IP-based chip