Design for diagnosis to improve IC yield

By Geir Eide, Mentor Graphics Inc.
edadesignline.com (January 25, 2010)

As integrated circuits grow in content and complexity, reaching target yield levels becomes challenging. A product engineer's worst nightmares frequently become reality: sample devices are supposed to be delivered to a demanding customer next week but they don't work on the tester. Yield is still in the single-digit range, and the product needs to be in stores for the holiday season. A large handful of failing devices were carefully selected and sent to failure analysis, but no problem was found.

Although scan diagnosis is an established, automated technique for localizing defects for failure analysis (FA), raising silicon production yield, and assisting first silicon debug, it's often an afterthought and taken for granted. Like a spare tire, it's ignored until you have a flat on an isolated forest road, then you realize that although you thought you were prepared, the spare tire is deflated and the lug wrench is missing.

A spare tire is more useful if it's maintained with sufficient air pressure. Just as well, to get the full benefit from diagnosis, certain requirements have to be understood and considered earlier during the design process, before there's a problem. If ignored, the diagnosis process can be unnecessarily complex or even unfeasible. As a result, the time to finding the root cause of yield loss may be unnecessarily long, failure analysis results may take longer time to produce, and time to production volumes may be delayed.

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