English
Early verification cuts design time and cost in algorithm-intensive systems
By Ken Karnofsky, senior strategist for signal processing applications, The MathWorks
edadesignline.com (January 22, 2010)
Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases.
It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Formal-based methodology cuts digital design IP verification time
- IP Verification : Building systems at the silicon level: time, cost, design constraints
- How to Save Time and Improve Communication Between Semiconductor Design and Verification Engineers
- Early Interactive Short Isolation for Faster SoC Verification
- System on Modules (SOM) and its end-to-end verification using Test Automation framework
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow