Retargeting IP -> Clearing ASIC obsolescence hurdles

One area where ASIC technology has gained widespread use is in the implementation of digital intermediate frequency (IF) circuits for radio communication systems. While the use of ASICs in a digital IF application is commonplace, the procedure for creating such an application is rigorous.

As a design progresses from concept to creation, ASIC engineers must work through a complex verification process. In a typical design flow, an application undergoes intense up-front design and simulation to ensure the operation and performance of the ASIC. This phase of the verification process, although time consuming, must be done before the ASIC is fabricated. The fabrication process itself can take several months, depending on a foundry's backlog and capacity. The resulting device, after being tested post -fabrication by the ASIC vendor, is ready for integration into an actual product. Minor bug fixes are possible after prototypes are made, but essentially the design is final at this point unless the ASIC user wants to undergo a second pass of the design, a costly and time-consuming option. Bug fixes and work-arounds are usually delegated to the system hardware and software external to the ASIC. It can often take several months to integrate the ASIC into the final product.

After completing the digital IF application, the user/sponsor may or may not "own" the design. Certainly the specific design is the property of the company that procured the ASIC, but the silicon IP used in the device may be owned, largely, by the ASIC vendor. The ASIC vendor may well control any future reuse of the design, in a different form or for a different application. The user who wishes to modify the design for a new application and reuse the IP must pay for it again.

The limitations

Clearly, this technology, while indispensable in many applications, imposes limitations on its use. The time required to complete the development of an ASIC, especially for a complex application such as digital IF, often conflicts with the compressed time-to-market focus of product development. The inability of developers to freely reuse ASIC vendor IP for new applications, and the problems caused when a process becomes obsolete, are all reasons engineers have looked to alternatives to ASIC technology.

Historically, the DSP building blocks needed to support a digital IF processing system have not been readily available as generic IP for end users to customize. Blocks such as numerically controlled oscillators (NCOs), digital mixers, finite impulse response (FIR) filters and digital phase-locked loops (PLLs) tended to be design efforts of their own and not widely available as parameterized, drop-in commodities for system use.

Until recently, there have been few alternatives to ASICs for creating cost-effective, high-performance DSP systems. While suitable for baseband (kilohertz) sampling rates, fixed-point software DSPs generally become swamped when called on to perform symbol processing at significantly higher (megahertz) rates. Earlier generations of programmable logic devices (PLDs) have also lacked the ability to replace ASICs in this domain because of their relatively low level of integration. The most recent generation of high-density programmable logic is up to the task, however, and PLD vendors are actively supporting DSP designs in a variety of ways. As a result, today's feature-rich PLDs can replace ASICs in many high-performance DSP applications. Targeting a DSP design to programmable logic can insulate it from the problems associated with ASIC technology.

Programmable logic vendors have the silicon to support ASIC-level complexity and the design environments to support entry and simulation of complex DSP designs such as a digital IF. For example, the APEX 20KE famil y of programmable logic devices from Altera Corp. (San Jose, Calif.) has the ability to support the high-rate processing logic needed to implement a digital IF for a multiband communications system. The APEX 20KE devices have features such as embedded memory for FIR filter coefficient storage and digital PLLs for processing clock generation.

Recently, there has been a significant proliferation of retail IP designed for programmable logic from Altera Corp. and third-party vendors. The IP, some of which is instantiated with silicon compilers, can be used to generate DSP building blocks, such as NCOs and FIR filters. An NCO is used to generate and adjust a high-resolution local-oscillator waveform. The oscillator is programmed to the center of the information band of a received IF signal. The local oscillator and receive IF signal are mixed to form a complex (in-phase and quadrature) signal at lower spectral band that is suitable for further processing. A silicon compiler, or "megawizard," also supports the IP provided by Altera to create a mixer, a combination of multiplication and addition primitives. The wizard allows a designer to specify the arithmetic primitives' parameters such as input register width. Likewise, the FIR filter compiler from Altera Corp. can be used to customize a filter block's parameters such as input and output precision and architecture.

With these types of off-the-shelf IP available, the basic architecture of a digital IF can be rapidly prototyped and simulated. Design priorities can be focused on the specific requirements of the application. System characteristics of the design, such as symbol width, sampling rate and frequency resolution can be established and modified during the design process.