Arrgghh! My FPGA's not working: Problems with the RTL

Addressing the current crisis with regard to debugging FPGA designs

By Clive Maxfield
pldesignline.com (February 02, 2010)

Maybe you're an ASIC designer forced by short product lifecycles to move into FPGAs. Or perhaps you're a team leader whose latest project requires chip-level integration, and an FPGA implementation seems to be the obvious choice. Or possibly you're actually used small- and medium-sized FPGAs in the past, but your new project requires you to push the envelope with the newest, highest-performing, highest-capacity FPGA architectures.

The problem is that you've been led to believe that getting a design to work on an FPGA is relatively simple. How hard could it be? All you have to do is capture the design, simulate it, synthesize it, load the resulting configuration file into the FPGA, test the result, modify the design, and repeat...

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