Guidelines for complex SoC verification

A plan-manage-execute approach to verification

By Jignesh Oza, eInfochips
edadesignline.com (February 15, 2010)

Almost 60-70% of time in the ASIC cycle is occupied by Functional Verification and so, the main aim of this paper is to provide overall guidelines in verification. More specifically, on the adoption of various planning strategies, managing the dynamics in projects and a metric-driven execution approach with the maximum possible automation and reusability that helps deliver a quality product on time and achieve silicon success.

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