Register File with low power retention mode and 3 speed options
High-Performance DSPs -> Serial interconnects back high-performance computing
![]() |
Serial interconnects back high-performance computing
By Steve Paavola, Director of Advanced Development, Sky Computers Inc., Chelmsford, Mass., EE Times
January 4, 2002 (7:23 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011115S0062
Related Articles
- Tutorial: Programming High-Performance DSPs, Part 1
- How to tackle serial backplane challenges with high-performance FPGA designs
- Platform FPGA design for high-performance DSPs
- High-Performance DSPs -> DSPs tread many paths to raise performance
- High-Performance DSPs -> AltiVec power: PCI buses fall short
New Articles
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |