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Aeonic Generate Digital PLL for multi-instance, core logic clocking
High-Performance DSPs -> Serial interconnects back high-performance computing
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Serial interconnects back high-performance computing
By Steve Paavola, Director of Advanced Development, Sky Computers Inc., Chelmsford, Mass., EE Times
January 4, 2002 (7:23 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011115S0062
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